As is well known in the art, non-volatile memory (NVM) cells may have bits stored therein that may be read, such as by means of a sense amplifier. In general, the sense amplifier determines the logical value stored in the cell by comparing the output of the cell with a reference level. If the current output is above the reference, the cell is considered erased (with a logical value of 1) and if the current output is below the reference, the cell is considered programmed (with a logical value of 0). In terms of threshold voltage of the cell itself, programming a cell increases the threshold voltage of the cell, whereas erasing decreases the threshold voltage.
Different curent levels are associated with different logical states, and a NVM cell's current level may be correlated to the amount of charge stored in a charge storage region of the cell. The cell prior to the storing of any charge within a charge storage region may be referred to as “native” or in its “initial” state.
Generally, in order to determine whether an NVM cell is at a specific state, for example erased, programmed, or programmed at one of multiple possible program states within a multi-level cell (“MLC”), the cell's current level is compared to that of a reference cell whose current level is preset at a level associated with the specific state being tested for.
In the simplest case, a “program verify” reference cell with a current set at level defined as a “program verily” level may be compared to a cell being programmed (i.e. charged) in order to determine whether a charge storage area of the cell has been sufficiently charged so as to be considered “programmed.”
In the case where the cell is an MLC, the cell may have several possible program states, and one or more program reference cells, each with one or more different current levels corresponding to each of the NVM cell's possible program states, may be used to determine the state of the MLC.
For reading a cell, the current levels of one or more “read verify” reference cells may be compared to the current of the cell being read. An “erase verify” reference cell with a current set at a level defined as an “erase verify” level may be compared against a memory cell during an erase operation in order to determine when the memory cell's charge storage area has been sufficiently discharged so as to consider the cell erased.
Enough margins should be kept between the different reference levels so that the logical state interpretation is free of mistakes under the differrent operation conditions (e.g. temperature and voltages changes and retention of the stored charge). In the simplest case it is common to define the margin between the read level and the erase verify level as the “erase margin” and the margin between the read level and the program verify level as the “program margin”. The margin between the initial NVM cell level and the lowest reference level, usually the erase verify level, is reffer to as ‘cycle margin’ (“CM”). Other margins and levels may be defined for different purposes. In a MLC NVM, few margins and levels are defined to assure a correct operation and interpretation of the different levels.
The positioning of the different reference levels is accomplished using data extracted from the NVM array during manufacturing. That is, during the manufacturing process, after fabrication, an NVM array may be tested to determine the native current levels of each of its cells. The preseting of the reference level is made using this data.
As FIG. 1 shows, native threshold voltages, and hence native currents, distribution across an NVM array may be different in different segments of the NVM array. Native threshold voltage distributions on an array may be in the order of 0.7V or more across the array. However, the distributions across an array segment may be lower, for example 0.2V. Thus, establishing the lowest reference voltage to be slightly higher than the highest native threshold voltage of the array (e.g., native threshold voltage found in a NVM cell in segment 1D of FIG. 1) may result in a large CM for cells in array segments whose NVM cells have native threshold voltages relatively lower than those in the segment with the NVM cell having the highest native threshold voltage.